library ieee; 
use ieee.std_logic_1164.all;
entity t_trig is --описание работы Т-триггера
port (reset: in std_logic; 
clk: in std_logic; 
en: in std_logic;
d_out: out std_logic); 
end t_trig;
architecture beh of t_trig is
signal int_data: std_logic; 
begin
  process (clk, reset, en)
    begin
	if (reset = '0') then
          int_data <= '0';
        else
		  if (en = '1') then 
          if falling_edge(clk) 
	  then
	    int_data <= not int_data; 
	  end if; 
        end if;
		  end if;
  end process;
d_out <= int_data;
end beh;
library ieee; 
use ieee.std_logic_1164.all;

entity two_and is -- описание работы элемента 2И
port(in1, in2: in std_logic;
out1: out std_logic);
end two_and;
architecture beh1 of two_and is
begin
	out1 <= in1 and in2;
end beh1;
library ieee; 
use ieee.std_logic_1164.all;
entity dec_to7 is -- описание работы дешифратора, выход которого приходит на семисегментный индикатор
port (SW: in std_logic_vector(3 downto 0);  
      HEX0: out std_logic_vector (6 downto 0)); 
end dec_to7;
architecture beh of dec_to7 is
begin
      HEX0 <= "1000000" when SW = "0000" else
			"1111001" when SW = "0001" else
			"0100100" when SW = "0010" else
			"0110000" when SW = "0011" else
			"0011001" when SW = "0100" else
			"0010010" when SW = "0101" else
			"0000010" when SW = "0110" else
			"1111000" when SW = "0111" else
			"0000000" when SW = "1000" else
			"0010000" when SW = "1001" else
			"0001000" when SW = "1010" else
			"0000011" when SW = "1011" else
			"1000110" when SW = "1100" else
			"0100001" when SW = "1101" else
			"0000110" when SW = "1110" else
			"0001110"; 
  end beh;
library ieee; 
use ieee.std_logic_1164.all; 
entity counter is --описание работы счетчика
port ( KEY: in std_logic_vector (3 downto 0);
       SW: in std_logic_vector (1 downto 0);
       HEX0: out std_logic_vector (6 downto 0));
end counter;		 	
architecture beh2 of counter is
component t_trig
port(reset: in std_logic; 
clk: in std_logic; 
en: in std_logic;
d_out: out std_logic); 
end component;
component two_and
port(in1, in2: in std_logic;
out1: out std_logic);
end component;
component dec_to7
port (SW: in std_logic_vector(3 downto 0);  
      HEX0: out std_logic_vector (6 downto 0));
end component;
signal t1, t2, t3, t4: std_logic;
signal a1, a2, a3: std_logic;
signal todec: std_logic_vector (3 downto 0);

begin
tr1: t_trig
port map (SW(1), KEY(0), SW(0), t1);
ta1: two_and
port map (SW(0), t1, a1);
tr2: t_trig
port map (SW(1), KEY(0), a1, t2);
ta2: two_and
port map (a1, t2, a2);
tr3: t_trig
port map (SW(1), KEY(0), a2, t3);
ta3: two_and
port map (a2, t3, a3);
tr4: t_trig
port map (SW(1), KEY(0), a3, t4);
todec <= t4 & t3 & t2 & t1;
dec1: dec_to7
port map (todec, HEX0);
 end beh2;