LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_UNSIGNED.all; -- пакеты для преобразования типов
use IEEE.STD_LOGIC_ARITH.all; -- и логических операций

entity lab2 is
port ( A: in STD_LOGIC_VECTOR (7 downto 0);
B: in STD_LOGIC_VECTOR (7 downto 0);
clock: in STD_LOGIC;
sum : out STD_LOGIC_VECTOR (9 downto 0));
end lab2;

architecture beh of lab2 is
signal reg_A, reg_B: STD_LOGIC_VECTOR (7 downto 0);
signal reg_sum : STD_LOGIC_VECTOR (9 downto 0);
begin
process (clock)
variable int_sum : integer range 0 to 1023;
begin
if clock'event and clock = '1' then
reg_A <= A;
reg_B <= B;
int_sum:=CONV_INTEGER(reg_A)+CONV_INTEGER(reg_B);
end if;
reg_sum <= CONV_STD_LOGIC_VECTOR(int_sum,10);
end process;
sum <= reg_sum;
end beh;