library ieee;
use ieee.std_logic_1164.all;

entity dec2 is
    port (
        SW       : in  std_logic_vector(3 downto 0);
        CLOCK_50 : in  std_logic;
        LEDG     : out std_logic_vector(7 downto 0)
    );
end dec2;

architecture beh of dec2 is
begin
    process(CLOCK_50)
    begin
        if rising_edge(CLOCK_50) then
            if SW = "0000" then
                LEDG <= "00000000";
            elsif SW = "0001" then
                LEDG <= "00000001";
            elsif SW = "0010" then
                LEDG <= "00000010";
            elsif SW = "0011" then
                LEDG <= "00000011";
            elsif SW = "0100" then
                LEDG <= "00000100";
            elsif SW = "0101" then
                LEDG <= "00000101";
            elsif SW = "0110" then
                LEDG <= "00000110";
            elsif SW = "0111" then
                LEDG <= "00000111";
            elsif SW = "1000" then
                LEDG <= "00001000";
            elsif SW = "1001" then
                LEDG <= "00001001";
            elsif SW = "1010" then
                LEDG <= "00010000";
            elsif SW = "1011" then
                LEDG <= "00010001";
            elsif SW = "1100" then
                LEDG <= "00010010";
            elsif SW = "1101" then
                LEDG <= "00010011";
            elsif SW = "1110" then
                LEDG <= "00010100";
            else
                LEDG <= "00010101";
            end if;
        end if;
    end process;
end beh;