library ieee;
use ieee.std_logic_1164.all;

------------------------------------------------------------
-- T-триггер
------------------------------------------------------------
entity t_trig is
    port (
        reset : in  std_logic;   -- активный 0
        clk   : in  std_logic;
        en    : in  std_logic;
        q     : out std_logic
    );
end t_trig;

architecture beh of t_trig is
    signal int_data : std_logic := '0';
begin
    process(clk, reset)
    begin
        if reset = '0' then
            int_data <= '0';
        elsif falling_edge(clk) then
            if en = '1' then
                int_data <= not int_data;
            end if;
        end if;
    end process;

    q <= int_data;
end beh;

------------------------------------------------------------
-- Элемент 2И
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;

entity two_and is
    port (
        in1  : in  std_logic;
        in2  : in  std_logic;
        out1 : out std_logic
    );
end two_and;

architecture beh of two_and is
begin
    out1 <= in1 and in2;
end beh;

------------------------------------------------------------
-- Дешифратор 4 бит -> 7 сегментов
-- HEX0 активен по нулю
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;

entity dec_to7 is
    port (
        SW   : in  std_logic_vector(3 downto 0);
        HEX0 : out std_logic_vector(6 downto 0)
    );
end dec_to7;

architecture beh of dec_to7 is
begin
    HEX0 <= "1000000" when SW = "0000" else -- 0
            "1111001" when SW = "0001" else -- 1
            "0100100" when SW = "0010" else -- 2
            "0110000" when SW = "0011" else -- 3
            "0011001" when SW = "0100" else -- 4
            "0010010" when SW = "0101" else -- 5
            "0000010" when SW = "0110" else -- 6
            "1111000" when SW = "0111" else -- 7
            "0000000" when SW = "1000" else -- 8
            "0010000" when SW = "1001" else -- 9
            "0001000" when SW = "1010" else -- A
            "0000011" when SW = "1011" else -- b
            "1000110" when SW = "1100" else -- C
            "0100001" when SW = "1101" else -- d
            "0000110" when SW = "1110" else -- E
            "0001110";                      -- F
end beh;

------------------------------------------------------------
-- Верхний модуль счетчика
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;

entity counter is
    port (
        KEY  : in  std_logic_vector(3 downto 0);
        SW   : in  std_logic_vector(1 downto 0);
        HEX0 : out std_logic_vector(6 downto 0)
    );
end counter;

architecture beh of counter is

    component t_trig
        port (
            reset : in  std_logic;
            clk   : in  std_logic;
            en    : in  std_logic;
            q     : out std_logic
        );
    end component;

    component two_and
        port (
            in1  : in  std_logic;
            in2  : in  std_logic;
            out1 : out std_logic
        );
    end component;

    component dec_to7
        port (
            SW   : in  std_logic_vector(3 downto 0);
            HEX0 : out std_logic_vector(6 downto 0)
        );
    end component;

    signal t1, t2, t3, t4 : std_logic;
    signal a1, a2, a3     : std_logic;
    signal todec          : std_logic_vector(3 downto 0);

begin

    -- 1-й T-триггер: переключается всегда, когда Enable=1
    tr1: t_trig
        port map (
            reset => SW(1),
            clk   => KEY(0),
            en    => SW(0),
            q     => t1
        );

    -- Enable для 2-го триггера
    and1: two_and
        port map (
            in1  => SW(0),
            in2  => t1,
            out1 => a1
        );

    -- 2-й T-триггер
    tr2: t_trig
        port map (
            reset => SW(1),
            clk   => KEY(0),
            en    => a1,
            q     => t2
        );

    -- Enable для 3-го триггера
    and2: two_and
        port map (
            in1  => a1,
            in2  => t2,
            out1 => a2
        );

    -- 3-й T-триггер
    tr3: t_trig
        port map (
            reset => SW(1),
            clk   => KEY(0),
            en    => a2,
            q     => t3
        );

    -- Enable для 4-го триггера
    and3: two_and
        port map (
            in1  => a2,
            in2  => t3,
            out1 => a3
        );

    -- 4-й T-триггер
    tr4: t_trig
        port map (
            reset => SW(1),
            clk   => KEY(0),
            en    => a3,
            q     => t4
        );

    -- Собираем 4-битное число
    todec <= t4 & t3 & t2 & t1;

    -- Вывод на семисегментный индикатор
    dec1: dec_to7
        port map (
            SW   => todec,
            HEX0 => HEX0
        );

end beh;